PC-3000 Forum

Hello guys,

I recently acquired PC3000 FLASH and I'm exploring the software and reading the manuals for a more extensive compreension. So far this looks really amazing.

I've read a few test chips that were in the solbase and obviously the recovery went 100%.

But now I'm trying chips there aren't in the solbase and I would like to get a better understanding of how to deal with this specific type of issue. (Forgive me in advance for such a simple question)

I'm testing a tsop-48 with this information:

1x1 98D594BA 74134300, part size=2048Mb, page size=4320 bytes, block size=128 pages

When I use ECC this is what I get:

Detect ECC for PAGE = 4224 bytes
- 0 [528]
- 528 [528]
- 1056 [528]
- 1584 [528]
- 2112 [528]
- 2640 [528]
- 3168 [528]
- 3696 [528]

When I go for a raw recovery I find many files, everything looks near perfection but I'm having a small checked size and according to the manual in section: 6.4.3.25. Raw recovery mode I believe i'm failing to have my files reaching all the checkpoints in order for them to be complete.

I'm now following the attached checklist and after doing this steps, i'm still failing, I know i'm doing something stupid wrong but I can't figure out what.

I'm not looking for a quick fix for this test chip, but just to understand what basic mistake i'm making (besides lack of basic knowledge).

Thank you for your help

Without knowing what you have done so far its impossible to say.

I've read, corrected ECC, then followed the procedure on the attached image always checking for improvements with no luck.

I'm gonna keep trying.

That sheet is very useful and gives you the basic outlines. But these days chips tend to be quite complex in their layout. Although the SSS6677 is normally pretty basic. For example some, chips need to have typical interleave applied more than once. If the chip has more than one part sometimes you need to join by page, some chips join by dump etc etc. Did you try translator SSS6690?

Can you post a screenshot of where you are now.

I will, i'm taking a 4 hour nap before resuming learning.
The documentation was really usefull, I have some basic grasp of it, but every time I read it something new pops and makes sense

Hello.

SSS6677 is a pretty complex controller. I recommend you to leave a ticket in TS system. Our engineers will guide you.

Hey Roman. I checked this controller in Solbase and the solved ones look pretty standard.
What makes it so complex (for my education).

d_d_recovery wrote:Source of the post That sheet is very useful and gives you the basic outlines. But these days chips tend to be quite complex in their layout. Although the SSS6677 is normally pretty basic. For example some, chips need to have typical interleave applied more than once. If the chip has more than one part sometimes you need to join by page, some chips join by dump etc etc. Did you try translator SSS6690?

Can you post a screenshot of where you are now.

Hi again.

This is what gave me the best results (some files have same size vs checked size but still few open)

We have a translator for SSS6677. Please make a ticket and we will check it.

Roman_TS wrote:Source of the post We have a translator for SSS6677. Please make a ticket and we will check it.

I did. Just trying to avoid wasting support time on something that must be basic.